Add LLCC support for Nord - #992
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Shiraz Hashim (shashim-quic) merged 3 commits intoAug 21, 2026
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August 20, 2026 17:52
Add the system cache controller. All sixteen banks are listed, four per DDR slice at 0x100000 strides from slice + 0x800000, followed by the global broadcast OR/AND regions, which the driver expects at the reg indices right after the last bank. No ECC interrupt is described, as the Nord interrupt map does not expose one for the LLCC. The driver treats it as optional. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI) SCT table and limited to the POR use cases that have a unique SCID and a usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full ALGO_ALLOC0..3 set, so it uses the v6 register offsets. num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0 is four bits wide and cannot report sixteen banks; a wrong count makes the driver map a bank aperture in place of the broadcast region and abort on the first broadcast read. no_edac is set because the bootloader leaves the LLCC EDAC registers locked, as on Glymur. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Nord has four DDR slices with four MACH9 LLCC banks each, so it exposes sixteen bank regions plus the shared broadcast OR/AND pair. Add its compatible with a matching reg/reg-names group and raise the top level maxItems to eighteen. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
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Shiraz Hashim (shashim-quic)
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Enables the last level cache controller (system cache) on Nord: DT binding,
driver configuration, and the SoC DT node.
Nord's LLCC has four DDR slices with four banks each, so sixteen bank regions
plus the shared broadcast pair. Same layout Glymur already uses.
Patches
Notes
to the POR use cases that have a unique SCID.
avoid aborts on this target. Details are in the commit messages.