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Merged
Shiraz Hashim (shashim-quic) merged 3 commits into from
Aug 21, 2026
Merged

Add LLCC support for Nord #992

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f87e3cb
PENDING: arm64: dts: qcom: nord: Add LLCC node
Aug 20, 2026
4824f1d
PENDING: soc: qcom: llcc: Add LLCC configuration for Nord
Aug 20, 2026
9b7f0f1
PENDING: dt-bindings: cache: qcom,llcc: Add Nord compatible
Aug 20, 2026
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55 changes: 53 additions & 2 deletions Documentation/devicetree/bindings/cache/qcom,llcc.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ properties:
- qcom,hawi-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,nord-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
Expand All @@ -51,11 +52,11 @@ properties:

reg:
minItems: 1
maxItems: 14
maxItems: 18

reg-names:
minItems: 1
maxItems: 14
maxItems: 18

interrupts:
maxItems: 1
Expand Down Expand Up @@ -350,6 +351,56 @@ allOf:
- const: llcc3_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base

- if:
properties:
compatible:
contains:
enum:
- qcom,nord-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC6 base register region
- description: LLCC7 base register region
- description: LLCC8 base register region
- description: LLCC9 base register region
- description: LLCC10 base register region
- description: LLCC11 base register region
- description: LLCC12 base register region
- description: LLCC13 base register region
- description: LLCC14 base register region
- description: LLCC15 base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc6_base
- const: llcc7_base
- const: llcc8_base
- const: llcc9_base
- const: llcc10_base
- const: llcc11_base
- const: llcc12_base
- const: llcc13_base
- const: llcc14_base
- const: llcc15_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base

- if:
properties:
compatible:
Expand Down
40 changes: 40 additions & 0 deletions arch/arm64/boot/dts/qcom/nord.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -6401,6 +6401,46 @@
};
};
};

llcc: system-cache-controller@21800000 {
compatible = "qcom,nord-llcc";
reg = <0x0 0x21800000 0x0 0x100000>,
<0x0 0x21a00000 0x0 0x100000>,
<0x0 0x21c00000 0x0 0x100000>,
<0x0 0x21e00000 0x0 0x100000>,
<0x0 0x22800000 0x0 0x100000>,
<0x0 0x22a00000 0x0 0x100000>,
<0x0 0x22c00000 0x0 0x100000>,
<0x0 0x22e00000 0x0 0x100000>,
<0x0 0x23800000 0x0 0x100000>,
<0x0 0x23a00000 0x0 0x100000>,
<0x0 0x23c00000 0x0 0x100000>,
<0x0 0x23e00000 0x0 0x100000>,
<0x0 0x24800000 0x0 0x100000>,
<0x0 0x24a00000 0x0 0x100000>,
<0x0 0x24c00000 0x0 0x100000>,
<0x0 0x24e00000 0x0 0x100000>,
<0x0 0x20400000 0x0 0x100000>,
<0x0 0x20600000 0x0 0x100000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
"llcc4_base",
"llcc5_base",
"llcc6_base",
"llcc7_base",
"llcc8_base",
"llcc9_base",
"llcc10_base",
"llcc11_base",
"llcc12_base",
"llcc13_base",
"llcc14_base",
"llcc15_base",
"llcc_broadcast_base",
"llcc_broadcast_and_base";
};
};

tpdm-nsp0-cdsp-llm {
Expand Down
121 changes: 121 additions & 0 deletions drivers/soc/qcom/llcc-qcom.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1014,6 +1014,110 @@ static const struct llcc_slice_config kaanapali_data[] = {
},
};

static const struct llcc_slice_config nord_data[] = {
{
.usecase_id = LLCC_CPUSS,
.slice_id = 1,
.max_cap = 3072,
.priority = 0,
.bonus_ways = 0xff,
.activate_on_init = true,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CMPT,
.slice_id = 34,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPUHTW,
.slice_id = 11,
.max_cap = 512,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_GPU,
.slice_id = 12,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_MMUHWT,
.slice_id = 13,
.max_cap = 1024,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_CAMFW,
.slice_id = 20,
.max_cap = 512,
.priority = 2,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_ECC,
.slice_id = 26,
.max_cap = 1536,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.write_scid_en = true,
.write_scid_cacheable_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_WRCACHE,
.slice_id = 31,
.max_cap = 2048,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_LCPDARE,
.slice_id = 30,
.max_cap = 512,
.priority = 3,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.alloc_oneway_en = true,
.vict_prio = true,
}, {
.usecase_id = LLCC_COMPUTE1,
.slice_id = 22,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.vict_prio = true,
}, {
.usecase_id = LLCC_PCIE_TCU,
.slice_id = 15,
.max_cap = 0,
.priority = 1,
.fixed_size = true,
.bonus_ways = 0xff,
.activate_on_init = true,
.vict_prio = true,
},
};

static const struct llcc_slice_config sa8775p_data[] = {
{
.usecase_id = LLCC_CPUSS,
Expand Down Expand Up @@ -4444,6 +4548,17 @@ static const struct qcom_llcc_config glymur_cfg[] = {
},
};

static const struct qcom_llcc_config nord_cfg[] = {
{
.sct_data = nord_data,
.size = ARRAY_SIZE(nord_data),
.reg_offset = llcc_v6_reg_offset,
.edac_reg_offset = &llcc_v6_edac_reg_offset,
.num_banks = 16,
.no_edac = true,
},
};

static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
Expand Down Expand Up @@ -4711,6 +4826,11 @@ static const struct qcom_sct_config glymur_cfgs = {
.num_config = ARRAY_SIZE(glymur_cfg),
};

static const struct qcom_sct_config nord_cfgs = {
.llcc_config = nord_cfg,
.num_config = ARRAY_SIZE(nord_cfg),
};

static const struct qcom_sct_config qcs615_cfgs = {
.llcc_config = qcs615_cfg,
.num_config = ARRAY_SIZE(qcs615_cfg),
Expand Down Expand Up @@ -5649,6 +5769,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,hawi-llcc", .data = &hawi_sct_cfgs },
{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},
{ .compatible = "qcom,nord-llcc", .data = &nord_cfgs},
{ .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs},
{ .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs},
{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
Expand Down
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