cnn-accelerator

Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

Convolutional accelerator kernel, target ASIC & FPGA

A FPGA Based CNN accelerator, following Google's TPU V1.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

A DNN Accelerator implemented with RTL.

Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.

2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition

基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

Modified version of the "Explore the energy-efficient dataflow scheduling for neural networks. "

SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.

Small-scale FPGA-based Neural Processing Unit (CNN Accelerator) with INT8 systolic array matrix multiplication in Verilog.

CNN accelerator datapath components

A CNN processor that takes layers of CNN as input instruction and performs the respective operation.

Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.

Custom FPGA hardware accelerators for image processing (5x5 Convolution & Sobel Edge Detection) on the Zynq-7000 SoC using Verilog, AXI4-Stream, and PYNQ.

Synthesizable INT8 CNN accelerator with bit-exact Python/RTL verification and a replaceable MAC interface.

FPGA implementation of a quantized LeNet-5 CNN accelerator combining High-Level Synthesis (Vitis HLS) and hand-written RTL (VHDL) for an optimized streaming convolution architecture.

SystemVerilog CNN accelerator for the Zybo Z7-20 / Zynq-7000 with AXI-Lite control, Vivado bitstream flow, and Vitis bare-metal ARM software.

Verilog implementation of a CNN-style image processing pipeline with convolution, activation, pooling, and RTL-based verification.