SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.
fpga matrix-multiplication vivado systemverilog fashion-mnist cnn-accelerator deep-learning-hardware lenet5-cnn systoli
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Updated
Jul 29, 2026 - SystemVerilog