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freepdk45
Here are 3 public repositories matching this topic...
32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.
asic computer-architecture vlsi risc-v cadence-virtuoso drc tcl-scripts physical-design place-and-route freepdk45 cadence-innovus standard-cells cmos-logic lvs-calibre
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Updated
Aug 13, 2026 - Tcl
NCSU FreePDK45 Lookup Tables for use with analog_daddy python library
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Updated
Nov 6, 2023
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