openlane2

Here are 5 public repositories matching this topic...

Entropify / Entropic_R32-P5_RISC-V

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

Updated Sep 4, 2026
Python

Samizo-AITL / openlane2-sram

Star

OpenLane2 example project for integrating an SRAM hard macro and generating GDS.

eda sram gds vlsi physical-design openroad openlane sky130 openlane2 hard-macro

Updated Jan 21, 2026

AnilS454 / pe-asic-sky130

Star

Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2

asic gds vlsi drc physical-design openroad timing-closure sky130 openlane2

Updated Mar 13, 2026
Perl

Faraz-shaikh-9 / Timing-Aware-MAC-RTL-to-GDSII

Star

Timing-aware 2-stage pipelined MAC implemented from SystemVerilog RTL through ASIC physical design and GDSII using OpenLane/OpenROAD and SKY130.

rtl verilog systemverilog vlsi semiconductor vlsi-physical-design gdsii static-timing-analysis openroad chip-design openlane2 sky130-pdk

Updated Aug 27, 2026
Verilog

Complete RTL-to-GDSII implementation of a UART IP Core using Verilog HDL and the OpenLane2 ASIC design flow with the SkyWater SKY130 PDK. Includes RTL design, functional verification, synthesis, physical design, timing analysis, DRC/LVS verification, and final GDSII layout.

uart uart-verilog verilog-hdl yosys uart-protocol asic-verification uart-transmitter uart-receiver vlsi-design openroad asic-design openlane2

Updated Jul 31, 2026
Verilog

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openlane2

Here are 5 public repositories matching this topic...

Entropify / Entropic_R32-P5_RISC-V

Samizo-AITL / openlane2-sram

AnilS454 / pe-asic-sky130

Faraz-shaikh-9 / Timing-Aware-MAC-RTL-to-GDSII

shivam-du / uart-rtl-to-gdsii

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