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pyuvm

Here are 22 public repositories matching this topic...

ttchisholm / 10g-low-latency-ethernet

10G Low Latency Ethernet

fpga xilinx ethernet systemverilog cocotb pyuvm

Updated Jul 15, 2023
SystemVerilog

WilliamZhang20 / ECE298A-TPU

A custom AI chip to be taped out soon!

pytorch cocotb asic-verification ai-chips asic-design pyuvm

Updated Dec 20, 2025
Python

hurisson / pyuvm_primer

Examples for using pyuvm

python cocotb apb3 pyuvm

Updated Jun 5, 2024
Python

merledu / coco-rvtb

Generic testbench for RISC-V CPUs

riscv uvm cocotb pyuvm

Updated Dec 13, 2025
Python

fvutils / pyuvm-dataclasses

Apply dataclasses concept to testbench automation in Python

python functional-verification dataclasses pyuvm

Updated Oct 9, 2022
Python

npatsiatzis / fifo_asynchronous

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 8, 2023
Python

Robert-Riordan-UCD / 8_Bit_CPU_FPGA

An 8-bit CPU running on a TangNano 9k FPGA. Written in SystemVerilog and tested with PYUVM.

fpga systemverilog tangnano9k pyuvm

Updated Dec 9, 2025
Python

bhavanibedreshankar / tpe-tensor-processing-engine

An open-source, from-scratch AI accelerator: RTL, C++ golden model, and a full pyuvm/cocotb verification environment with 7 intentionally-catalogued bugs.

verification rtl systemverilog uvm digital-design cocotb hardware-verification design-verification pyuvm ai-accelerator

Updated Jul 31, 2026
Python

npatsiatzis / cdc_handshake

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / fir

vhdl systemverilog verilator cocotb sby pyuvm

Updated Oct 8, 2023
Python

npatsiatzis / uart

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
VHDL

npatsiatzis / recirculation_mux

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / moving_average

vhdl systemverilog verilator cocotb pyuvm

Updated Oct 8, 2023
Python

repowazdogz-droid / spcu-verification

Secure Power Control Unit verified with open tools (SymbiYosys, Verilator, pyuvm, bare-metal C). Formal found 4 unseeded RTL bugs, then mutation analysis showed 2 defects that pass every specification-derived property because the specification never stated the requirement.

mutation-testing specification systemverilog formal-verification verilator hardware-verification symbiyosys pyuvm

Updated Sep 2, 2026
SystemVerilog

npatsiatzis / bcd_bin_conv

vhdl cocotb pyuvm

Updated Oct 1, 2023
Python

npatsiatzis / fizzbuzz

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
Python

npatsiatzis / fifo_synchronous

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
C++

npatsiatzis / gray_bin_conv

vhdl cocotb pyuvm

Updated Oct 1, 2023
Python

Robert-Riordan-UCD / robs-risc-v

My 32I RISC-V implementation

cpu system-verilog risc-v riscv32i pyuvm

Updated Jul 6, 2026
Python

npatsiatzis / barrel_shifter

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 8, 2023
C++

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