test-bench-verification

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Pranav-2045 / CORDIC

A synthesizable 16-stage pipelined CORDIC engine in Verilog for high-throughput sine and cosine calculation. 🚀

fpga rtl verilog finite-state-machine icarus-verilog hardware-acceleration verilog-hdl xilinx-vivado cordic digital-logic-design pipelined cordic-algorithm synthesizable fixed-point-arithmetic gtk-wave test-bench-verification synthesizable-verilog verilog-2001 digital-verification

Updated Mar 24, 2026
Verilog

ThirupathiReddyPuchakayala / DESIGN-AND-IMPLEMENTATION-OF-1X3-ROUTER

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This project contains the RTL implementation and functional verification of a 1x3 packet router. Designed using Verilog HDL, the router accepts 8-bit data packets through a single input port and routes them to one of three output ports based on the packet header. The design includes modules such as input register, synchronizer, FSM controller...

router fpga rtl verilog digital-design test-bench-verification

Updated Jul 4, 2025
Verilog

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