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xcelium

Here are 10 public repositories matching this topic...

wavepeek

kleverhq / wavepeek

🌊 CLI tool for RTL waveform (VCD/FST/FSDB) inspection

waveform rtl vcs modelsim vcd fst icarus verilator cocotb fsdb xcelium

Updated Aug 23, 2026
Rust

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

kaushalmodi / custom_uvm_report_server

Customized UVM Report Server

vcs systemverilog synopsys uvm cadence xcelium

Updated Feb 10, 2020
SystemVerilog

tymonx / pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

python flow asic fpga vhdl tcl eda python3 rtl verilog xilinx vivado systemverilog hdl cadence xcelium

Updated Aug 11, 2025
Python

prernamittal / VerilogAlarmClock

This project implements a digital clock with alarm functionality in Verilog and SystemVerilog.

verilog systemverilog xcelium

Updated Jun 26, 2023
SystemVerilog

jacobpanov / Yapp_Router

UVM-Based Verification Project for a YAPP (Yet Another Packet Protocol) Router

systemverilog xcelium uvm-verification

Updated Mar 28, 2025
SystemVerilog

jawadsa02 / credit-arbiter-specman

Specman/e UVC for a credit-based multi-flow arbiter — independent checker, constrained traffic, Xcelium integration

eda systemverilog arbiter xcelium specman chip-verification

Updated Aug 26, 2026
E

jawadsa02 / networking-cluster-integration

Mixed-language UVM + VHDL networking cluster — dual-clock buffer, end-to-end scoreboard, live config

vhdl eda systemverilog uvm xcelium mixed-language chip-verification

Updated Aug 26, 2026
SystemVerilog

Gaya3Bhat / axi-lite-complaint-dual-mode-arbiter

Configurable AXI arbiter (Round Robin / Fixed Priority + Aging) — RTL verified in Vivado, implemented on Xilinx Artix-7, UVM testbench verified on Xcelium 25.03

fpga verification vivado systemverilog uvm axi xcelium hardware-design rtl-design-and-verification rtl-design-and-simulation

Updated Aug 28, 2026
SystemVerilog

jawadsa02 / qos-egress-scheduler-uvm

UVM verification of a programmable egress QoS scheduler — SP/WRR arbitration, reference model, SVA, coverage

eda systemverilog uvm qos xcelium chip-verification

Updated Aug 26, 2026
SystemVerilog

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