Invalid verilog generated with constant idx into ROM

[da-steve101]

With the following verilog, the always @(*) is interpreted as trigger on all input changes. However as there are no inputs, this never triggers. Hence it has the value xxx. This pr is a bit hacky but gets round it by changing the declaration to set the reg to an initial value.

reg [3:0] T0;
 always @(*) case (2'h2)
    0: T0 = 4'h3;
    1: T0 = 4'h1;
    2: T0 = 4'h5;
    3: T0 = 4'h8;
    default: begin
      T0 = 4'bx;
`ifndef SYNTHESIS
// synthesis translate_off
      T0 = {1{$random}};
// synthesis translate_on
`endif
    end
  endcase

instead have

reg [3:0] T0 = 4'h5;

[ghost]

Can one of the admins verify this patch?